(1). Field of the Invention
This invention relates to a data transfer apparatus or a data transfer system for arbitrating a plurality of I/O ports in data transfers, specifically to a data transfer apparatus or a data transfer system which transfers stream data in certain units between a plurality of I/O ports and a plurality of corresponding storage areas with the DMA (Direct Memory Access) method.
(2). Description of the Prior Art
Data transfer systems, which input/output stream data such as video data to/from a plurality of users, provide a demand-type service in which specified pieces of stream data are transferred based on transfer requests specifying users.
Such data transfer systems include mass storages such as HDDs (Hard Disk Drives) or optical disk drives for storing large amounts of stream data. A piece of stream data specified by a user is transferred from the mass storages via a channel, or vice versa. The channels are achieved by I/O ports which are respectively assigned to the users and used for transferring the stream data.
FIG. 1 is a block diagram showing a conventional data transfer system.
The conventional data transfer system is composed of CPU 10, memory 11, system bus 12, SCSI interface 13, HDDs 14a, 14b, 14c, and 14d, and stream interfaces 50a, 50b, 50c, and 50d. The drawing also shows external units: video monitors 16a, 16b, and 16c, and video cassette recorder 17.
CPU 10 generates commands required for transferring specified pieces of stream data based on the transfer requests for respective users and stores the commands in memory 11. CPU 10 also transfers the commands from memory 11 to stream interface 50a, 50b, 50c, or 50d.
Memory 11 stores the commands generated by CPU 10 and temporarily stores stream data during data transfers.
System bus 12 is connected to CPU 10, memory 11, system bus 12, SCSI interface 13, and stream interfaces 50a, 50b, 50c, and 50d and is used for transferring the stream data and the commands between these units. System bus 12 is achieved, for example, by a PCI (Peripheral Component Interconnect) bus which is a local bus standard. The bus width of the PCI bus is 32 bits or 64 bits and the operating frequency is 33 MHz. When the bus width is 32 bits and the operating frequency is 33 MHz, for example, the data transfer performance of the PCI bus is 133 MB/s.
SCSI interface 13 is connected to system bus 12 and HDDs 14a, 14b, 14c, and 14d. SCSI interface 13, on receiving a command from CPU 10 which is required for transferring stream data, transfers the stream data between memory 11 and each HDD via system bus 12, based on the command.
HDDs 14a, 14b, 14c, and 14d store stream data.
Stream interface 50a is connected to system bus 12 and video monitor 16a. Stream interface 50b is connected to system bus 12 and video monitor 16b. Stream interface 50c is connected to system bus 12 and video monitor 16c. Stream interface 50d is connected to system bus 12 and video monitor 16d.
Each stream interface, on receiving a command required for transferring the stream data from CPU 10, transfers the stream data between memory 11 and each external unit via system bus 12, based on the command. The connection between each stream interface and each external unit conforms to, for example, IEEE1394 which is a standard for serial digital transfer. The IEEE standard allows data transfer at a rate of 100 Mbps at the maximum. That means, it has enough capacity for transferring image information at a rate of 30 Mbps.
In general, the SCSI interface 13 and the stream interfaces use the DMA transfer method for transferring data. Japanese Laid-Open Patent Application No.5-151146 ("DMA Transfer Method") discloses a DMA transfer method. This conventional technique includes a means for tracing an address and a data length for the data transfer next in order so that a plurality of DMA transfers are executed with only one activation of CPU. Such a "chained" DMA transfer is suitable for sequentially transferring a large amount of high bit-rate stream data, such as image information.
Japanese Laid-Open Utility Model No.3-54058 ("DMA Control Circuit") discloses a method for DMA-transferring data between an input/output unit and a memory which is managed with the virtual storage method. Note that the term "DMA-transferring" used in the present description indicates transferring data with the DMA (Direct Memory Access) method. This conventional technique discloses executing a "chained" DMA transfer which enables a sequential transfer of data stored in the memory managed by the virtual storage method.
Japanese Laid-Open Patent Application No.6-250965 ("Input/Output Control Apparatus") discloses a method for DMA-transferring data between a plurality of input/output units and a memory. This conventional technique discloses holding of a plurality of commands and a status, which improves the effectiveness of the process.
Japanese Laid-Open Patent Application No.5-334232 ("DMA Transfer Control Apparatus") discloses a method for DMA-transferring data between a plurality of input/output units and a memory achieved by a DRAM (Dynamic Random Access Memory device). This conventional technique discloses presetting of the number of accesses, which balances the amounts of data transferred by the plurality of input/output units and the memory, increasing the memory accesses in the high-speed access mode which is provided by the DRAM, and improving the effectiveness of the data transfer.
The above conventional data transfer system has the following characteristics.
Firstly, for the data transfers between an HDD and a memory or between a memory and a stream interface, the stream data, which is stored in sequence, is read in units of blocks. This increases the effectiveness in data reading, increases the amount of data processed for each data reading, and increases the data transfer rate as a whole, where the data transfer rate indicates the amount of data transferred per unit time. For example, data transfer rate of 20 MB/s is achieved by an HDD with an interface conforming to the Fast Wide SCSI standard. Accordingly, the above effects reduce the time period during which the system bus is occupied by a data transfer, resulting in an effective use of the system bus.
Secondly, the data transfer rate in each channel is lower than that for data transfer between an HDD and a memory or between a memory and a stream interface. For example, the data transfer rate for image information compressed under the MPEG1 standard is 1.5 Mbps (=0.1875 MB/s). Also, the data transfer rate for compressed high-quality image information is about 30 Mbps (=3.75 MB/s).
The above data transfer rates indicate that a plurality of pieces of image information can be transferred in parallel by one data transfer system.
Such image information is managed in units of frames. Generally 30 frames of image information correspond to the images reproduced in one second. Also, frame pulses are used for indicating each separated frame.
However, the above conventional technique has a few problems. That is, it is impossible for the conventional technique to secure that each piece of the stream data is output to each of a plurality of I/O ports in real time. Also, a display image is disturbed if the transferred image information is broken for more than a certain time period. Especially, this tends to happen when a plurality of pieces of image information are output.